1. Field of the invention
The present invention relates to a tester for semiconductor chips, and more particularly to a tester for semiconductor chips which are applicable to semiconductor chips having a plurality of pins.
2. Description of the Prior Art
Generally, functional tests for finished semiconductor chips are carried out in such a manner that pads of a semiconductor chip are in contact with corresponding external probe tips to flow current through it followed by an output from the semiconductor chip being checked.
Referring to FIG. 1, there is shown a conventional tester adapted to achieve a functional test of semiconductor chips. The tester comprises aluminum pads 3 which are exposed outwardly of a passivation layer 2 applied to a semiconductor chip 1, probe tips 4 of metal wires adapted to come into contact with respective corresponding aluminum pads 3 and probe wires 5 each connected at one end thereof to each corresponding probe tip 4 and at the other end thereof a test card (not shown). The reference numeral 6 denotes a microscope for inspecting the semiconductor chip 1 to dispose it at a predetermined position.
Operation of the above tester for semiconductor chips will be now described. First, the semiconductor chip 1 is placed on a testing mount 7 and the probe tips 4 each placed in position on the corresponding aluminum pad 3 by movement of the semiconductor chip 1 while carrying out an inspection by means of the microscope. Thereafter, an electrical property/of the semiconductor chip is checked by the test card which is connected to the aluminum pad 3 on the semi conductor 1 via the probe wires 5.
The conventional tester for semiconductor chips has fine probe tips. However, since probe wires connected to the probe tips have large diameter and thus occupy large space, the tester is hard to have many probe tips and to test simultaneously a plurality of pins of a semiconductor chip. In other words, although the conventional tester is capable of testing a semiconductor chip having a few of pins, it can not do simultaneously probings for semiconductor chip having many pins such as a logic tip. This is because the tester has insufficient space to make probe tips come into contact with all pins of the semiconductor chip.